This application claims priority under 35 USC §119 to Korean Patent Application No. 2007-0040582, filed on Apr. 25, 2007 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to liquid crystal display (LCD) devices, and more particularly to an LCD device having alternating layouts of sub-pixels for reducing vertical faults in the LCD device.
2. Background of the Invention
Generally, a liquid crystal display (LCD) device has a resolution depending on the number of integrated pixels. As the size of the LCD increases, the resolution also increases. For displaying high-quality images, the resolution has been increased with higher integration of pixels in a liquid crystal panel.
For overcoming limitations of liquid crystal response speed, flicker, and lag (or after-image) in high-definition or large-screen LCD devices (e.g., LCD televisions), driving a LCD device at a higher frame rate of 120 Hz instead of a frame rate of 60 Hz has been suggested. However, if 1-dot inversion or 2-dot inversion is used in the LCD device driven at the higher frame rate of 120 Hz, luminance is decreased due to charge deficit, and securing a driving margin is difficult because of gate line delay.
Accordingly, conventional LCD devices use column inversion for securing driving margin despite gate line delay. Therefore, liquid crystal panels using super patterned vertical alignment (S-PVA) with a 1 gate and 2 data (1G2D) structure are driven at a frame rate of 120 Hz with column inversion.
FIG. 1 illustrates a layout of sub-pixels in a conventional liquid crystal panel 10 having super patterned vertical alignment (S-PVA) with a 1G2D structure, in which each pixel is connected to a single gate line and two data lines. Referring to FIG. 1, the liquid crystal panel 10 includes a plurality of gate lines GY1, GY2, and GY3, a plurality of data lines SY1, SY2, SY3, SY4, SY5, and SY6, and a plurality of pixels each including a respective first sub-pixel A and a respective second sub-pixel B.
Each pixel includes a respective first switching element T1 and a respective second switching element T2. The switching elements T1 and T2 are for example NMOSFETs (N-channel metal oxide semiconductor field effect transistors) with each having a respective gate connected to a respective one of the gate lines GY1, GY2, and GY3, and each having a respective drain/source connected to a respective one of the data lines SY1, SY2, SY3, SY4, SY5, and SY6. Each of the switching elements T1 and T2 provides a respective data signal received from such a respective data line to a respective one of the first sub-pixel A and the second sub-pixel B.
The data lines SY1, SY2, SY3, SY4, SY5, and SY6 are paired into adjacent data lines forming a data line pair, e.g., SY1 and SY2, SY3 and SY4, or SY5 and SY6. Each data line pair is connected to the respective two sub-pixels of one pixel for providing respective data signals from a data driver (not shown). For example, one data line SY1 of a data line pair (SY1 and SY2) provides a respective data signal to the first sub-pixel A via the first switching element T1, and the other data line SY2 of such a data line pair provides a respective data signal to the second sub-pixel B via the second switching element T2.
FIG. 2 illustrates voltage polarities of data signals generated from the data driver (not shown) when the liquid crystal panel 10 of FIG. 1 is driven using column inversion. FIG. 3 illustrates voltage polarities as displayed via the sub-pixels A and B on the liquid crystal panel 10 of FIG. 1.
Referring to FIG. 1, a first area of the first sub-pixel A is greater toward a left side of each pixel, and a second area of the second sub-pixel B is greater toward a right side of each pixel in the liquid crystal panel 10. In addition referring to FIGS. 1, 2, and 3, the first data line SY1 that is driven with the positive polarity voltage results in the first sub-pixels A dominating luminance with bias of such positive polarity voltage toward the left side of a first column of pixels. Furthermore, the second data line SY2 that is driven with the negative polarity voltage results in the second sub-pixels B dominating luminance with bias of such negative polarity voltage toward the right side of the first column of pixels.
Additionally, the third data line SY3 that is driven with the negative polarity voltage results in the first sub-pixels A dominating luminance with bias of such negative polarity voltage toward the left side of a second column of pixels. Furthermore, the fourth data line SY4 that is driven with the positive polarity voltage results in the second sub-pixels B dominating luminance with bias of such positive polarity voltage toward the right side of the second column of pixels.
Thus in FIG. 3, each rectangle represents a respective one of the sub-pixels A and B that dominates luminance from having larger area toward each of the left and right sides of a pixel. Thus, two horizontally adjacent rectangles in FIG. 3 represent respective first and second sub-pixels A and B dominating luminance toward the left and right sides of one pixel in FIG. 1.
Such biasing of the sub-pixels of subsequent columns of the liquid crystal panel 10 is repeated to result in FIG. 3 according to column inversion. Referring to FIG. 4, when a common voltage applied to the liquid crystal panel 10 is shifted from Vcom0 to Vcom1, a magnitude of a positive polarity voltage V+ is different from a magnitude of a negative polarity voltage V−, resulting in common voltage asymmetry.
With such common voltage asymmetry, charge accumulation and thus luminance becomes different between the sub-pixels having the positive polarity voltage V+ applied thereon and the sub-pixels having the negative polarity voltage V− applied thereon, especially when the liquid crystal panel 10 is driven at low gradation and low frequency. In addition, when each frame is displayed in a predetermined pattern (e.g., a pattern that is shifted in units of even dots as illustrated in FIG. 5) in the liquid crystal panel 10 driven using column inversion, the border of the pattern maintains the same polarity with induced luminance difference such that a vertical fault occurs.